Designing and fabricating electronic systems typically involves many steps, known as a design flow. The particular steps of a design flow often are dependent upon the type of electronic system being designed, its complexity, the design team, and the fabricator or foundry that will manufacture the electronic system. The design flow typically starts with a specification for a new electronic system, which can be transformed into a logical design. The logical design can model the electronic system at a register transfer level (RTL), which is usually coded in a Hardware Design Language (HDL), such as System Verilog, Very high speed integrated circuit Hardware Design Language (VHDL), System C, or the like. The logical design of the electronic system can be analyzed to confirm that it will accurately perform the functions desired for the electronic system. This analysis is sometimes referred to as “functional verification.”
After the accuracy of the logical design is confirmed, it can be converted into a device design by synthesis software. The device design, which is typically in the form of a schematic or netlist, describes the specific components, such as transistors, resistors, and capacitors, which can be used in the electronic system, along with their interconnections. This device design generally corresponds to the level of representation displayed in conventional circuit diagrams.
A designer, for example, using a place-and-route tool, can place portions of the device design relative to each other in a geographic design environment. While these device design portions can correspond to segments of code in a hardware description language, they typically are shown in the geographic design environment as blocks representing components of the electrical system. Once the blocks have been placed relative to each other, wiring lines can be routed between the blocks. These wiring lines represent the interconnections, such as data signal interconnections and clock signal interconnections, which can be formed between the components of the electrical system.
These clock signal interconnections, often referred to as a clock tree, are typically synthesized by the place-and-route tool based on manually-defined timing constraints for the device design. A static timing analysis tool can analyze the synthesized clock tree to determine clock signal delay at each node in the clock tree of the device design in the geographic design environment. When the clock signal delays fall outside of timing requirements of the device design, often called a timing violation, the designer can identify portions of the clock tree causing the timing violation and modify timing constraints utilized to synthesize the clock tree. This process of synthesizing the clock tree based on timing constraints, performing static timing analysis on the synthesized clock tree, and, when there is a timing violation, revising the timing constraints can be performed iteratively in an attempt to generate a clock tree without timing violations.
While much of the design effort to remedy the presence of a timing violation in a synthesized clock tree is manual, the place-and-route tool can provide textual reports and present a table representation of the clock tree for use by a designer to identify portions of the clock tree causing the timing violation. These table representations of the clock tree often include icons corresponding to nodes in the clock tree that, when selected, can expand to identify upstream or downstream clock tree nodes, allowing the designer to review discrete branches in clock tree. Many modern clock trees, however, have complex structures, for example, including clock loops, clock convergence nodes, or the like, which are obfuscated in the table representation.